/*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by Paul Fleischer * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* Derived from s3c2410reg.h */ /* * Copyright (c) 2003, 2004 Genetec corporation. All rights reserved. * Written by Hiroyuki Bessho for Genetec corporation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of Genetec corporation may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* * Samsung S3C2440X processor is ARM920T based integrated CPU * * Reference: * S3C2440X User's Manual */ #ifndef _ARM_S3C2XX0_S3C2440REG_H_ #define _ARM_S3C2XX0_S3C2440REG_H_ /* common definitions for S3C2800, S3C2400 and S3C2410 */ #include /* common definitions for S3C2400 and S3C2410 */ #include /* * Memory Map */ #define S3C2440_BANK_SIZE 0x08000000 #define S3C2440_BANK_START(n) (S3C2440_BANK_SIZE*(n)) #define S3C2440_SDRAM_START S3C2440_BANK_START(6) /* * Physical address of integrated peripherals */ #define S3C2440_MEMCTL_BASE 0x48000000 /* memory controller */ #define S3C2440_USBHC_BASE 0x49000000 /* USB Host controller */ #define S3C2440_INTCTL_BASE 0x4a000000 /* Interrupt controller */ #define S3C2440_DMAC_BASE 0x4b000000 #define S3C2440_DMAC_SIZE 0xe4 #define S3C2440_CLKMAN_BASE 0x4c000000 /* clock & power management */ #define S3C2440_LCDC_BASE 0x4d000000 /* LCD controller */ #define S3C2440_NANDFC_BASE 0x4e000000 /* NAND Flash controller */ #define S3C2440_NANDFC_SIZE 0x18 #define S3C2440_UART0_BASE 0x50000000 #define S3C2440_UART_BASE(n) (S3C2440_UART0_BASE+0x4000*(n)) #define S3C2440_TIMER_BASE 0x51000000 #define S3C2440_USBDC_BASE 0x5200140 #define S3C2440_USBDC_SIZE 0x130 #define S3C2440_WDT_BASE 0x53000000 #define S3C2440_IIC_BASE 0x54000000 #define S3C2440_IIS_BASE 0x55000000 #define S3C2440_GPIO_BASE 0x56000000 #define S3C2440_GPIO_SIZE 0xd0 #define S3C2440_RTC_BASE 0x57000000 #define S3C2440_RTC_SIZE 0x8B #define S3C2440_ADC_BASE 0x58000000 #define S3C2440_ADC_SIZE 0x18 #define S3C2440_SPI0_BASE 0x59000000 #define S3C2440_SPI1_BASE 0x59000020 #define S3C2440_SDI_BASE 0x5a000000 /* SD Interface */ #define S3C2440_SDI_SIZE 0x44 /* interrupt control (additional defs for 2440) */ #define ICU_LEN (32+11) #define INTCTL_SUBSRCPND 0x18 /* sub source pending (2410+2440 only) */ #define INTCTL_INTSUBMSK 0x1c /* sub mask (2410+2440 only) */ /* 2440 has more than 32 interrupt sources. These are sub-sources * that are OR-ed into main interrupt sources, and controlled via * SUBSRCPND and SUBSRCMSK registers */ #define S3C2440_SUBIRQ_MIN 32 #define S3C2440_SUBIRQ_MAX (32+10) /* cascaded to INT_ADCTC */ #define S3C2440_INT_ADC (S3C2440_SUBIRQ_MIN+10) /* AD converter */ #define S3C2440_INT_TC (S3C2440_SUBIRQ_MIN+9) /* Touch screen */ /* cascaded to INT_UART2 */ #define S3C2440_INT_ERR2 (S3C2440_SUBIRQ_MIN+8) /* UART2 Error interrupt */ #define S3C2440_INT_TXD2 (S3C2440_SUBIRQ_MIN+7) /* UART2 Tx interrupt */ #define S3C2440_INT_RXD2 (S3C2440_SUBIRQ_MIN+6) /* UART2 Rx interrupt */ /* cascaded to INT_UART1 */ #define S3C2440_INT_ERR1 (S3C2440_SUBIRQ_MIN+5) /* UART1 Error interrupt */ #define S3C2440_INT_TXD1 (S3C2440_SUBIRQ_MIN+4) /* UART1 Tx interrupt */ #define S3C2440_INT_RXD1 (S3C2440_SUBIRQ_MIN+3) /* UART1 Rx interrupt */ /* cascaded to INT_UART0 */ #define S3C2440_INT_ERR0 (S3C2440_SUBIRQ_MIN+2) /* UART0 Error interrupt */ #define S3C2440_INT_TXD0 (S3C2440_SUBIRQ_MIN+1) /* UART0 Tx interrupt */ #define S3C2440_INT_RXD0 (S3C2440_SUBIRQ_MIN+0) /* UART0 Rx interrupt */ #define S3C2440_INTCTL_SIZE 0x20 /* Clock control */ #define CLKMAN_LOCKTIME 0x00 #define CLKMAN_MPLLCON 0x04 #define CLKMAN_UPLLCON 0x08 #define CLKMAN_CLKCON 0x0c #define CLKCON_SPI (1<<18) #define CLKCON_IIS (1<<17) #define CLKCON_IIC (1<<16) #define CLKCON_ADC (1<<15) #define CLKCON_RTC (1<<14) #define CLKCON_GPIO (1<<13) #define CLKCON_UART2 (1<<12) #define CLKCON_UART1 (1<<11) #define CLKCON_UART0 (1<<10) /* PCLK to UART0 */ #define CLKCON_SDI (1<<9) #define CLKCON_TIMER (1<<8) /* PCLK to TIMER */ #define CLKCON_USBD (1<<7) /* PCLK to USB device controller */ #define CLKCON_USBH (1<<6) /* PCLK to USB host controller */ #define CLKCON_LCDC (1<<5) /* PCLK to LCD controller */ #define CLKCON_NANDFC (1<<4) /* PCLK to NAND Flash controller */ #define CLKCON_IDLE (1<<2) /* 1=transition to IDLE mode */ #define CLKCON_STOP (1<<0) /* 1=transition to STOP mode */ #define CLKMAN_CLKSLOW 0x10 #define CLKMAN_CLKDIVN 0x14 #define CLKDIVN_HDIVN_MASK 0x6 #define CLKDIVN_HDIVN_SHIFT 1 #define CLKDIVN_PDIVN (1<<0) /* pclk=hclk/2 */ #define CLKMAN_CAMDIVN 0x18 #define CLKCAMDIVN_HCLK4_HALF (1<<8) /* Modifies HDIVN division rate if CLKDIVN[2:1] == 10b*/ #define CLKCAMDIVN_HCLK3_HALF (1<<9) /* Modifies HDIVN division rate if CLKDIVN[2:1] == 11b*/ /* NAND Flash controller */ #define NANDFC_NFCONF 0x00 /* Configuration */ #define NANDFC_NFCMD 0x08 /* command */ #define NANDFC_NFADDR 0x0C /* address */ #define NANDFC_NFDATA 0x10 /* data */ #define NANDFC_NFSTAT 0x20 /* operation status */ #define NANDFC_NFECC 0x34 /* ecc */ /* GPIO */ #define GPIO_PACON 0x00 /* port A configuration */ #define PCON_INPUT 0 /* Input port */ #define PCON_OUTPUT 1 /* Output port */ #define PCON_ALTFUN 2 /* Alternate function */ #define PCON_ALTFUN2 3 /* Alternate function */ #define GPIO_PADAT 0x04 /* port A data */ #define GPIO_PBCON 0x10 #define GPIO_PBDAT 0x14 #define GPIO_PBUP 0x18 #define GPIO_PCCON 0x20 #define GPIO_PCDAT 0x24 #define GPIO_PCUP 0x28 #define GPIO_PDCON 0x30 #define GPIO_PDDAT 0x34 #define GPIO_PDUP 0x38 #define GPIO_PECON 0x40 #define GPIO_PEDAT 0x44 #define GPIO_PEUP 0x48 #define GPIO_PFCON 0x50 #define GPIO_PFDAT 0x54 #define GPIO_PFUP 0x58 #define GPIO_PGCON 0x60 #define GPIO_PGDAT 0x64 #define GPIO_PGUP 0x68 #define GPIO_PHCON 0x70 #define GPIO_PHDAT 0x74 #define GPIO_PHUP 0x78 #define GPIO_MISCCR 0x80 /* miscellaneous control */ #define GPIO_DCLKCON 0x84 /* DCLK 0/1 */ #define GPIO_EXTINT(n) (0x88+4*(n)) /* external int control 0/1/2 */ #define GPIO_EINTFLT(n) (0x94+4*(n)) /* external int filter control 0..3 */ #define GPIO_EINTMASK 0xa4 #define GPIO_EINTPEND 0xa8 #define GPIO_GSTATUS0 0xac /* external pin status */ #define GPIO_GSTATUS1 0xb0 /* external pin status */ #define GPIO_SET_FUNC(v,port,func) \ (((v) & ~(3<<(2*(port))))|((func)<<(2*(port)))) #define GPIO_SET_DATA(v,pin,val) \ ( ((v) & ~(1<> SDIDATCNT_BLK_NUM_CNT_SHIFT) #define SDI_DAT_STA 0x34 #define SDIDATSTA_RX (1 << 0) #define SDIDATSTA_TX (1 << 1) #define SDIDATSTA_BUSY_FIN (1 << 3) #define SDIDATSTA_DATA_FIN (1 << 4) #define SDIDATSTA_DATA_TIMEOUT (1 << 5) #define SDIDATSTA_CRC_DAT_FAIL (1 << 6) #define SDIDATSTA_CRC_STATUS_FAIL (1 << 7) #define SDIDATSTA_SDIO_INT (1 << 9) #define SDIDATSTA_RWAIT_REQ (1 << 10) #define SDIDATSTA_NO_BUSY (1 << 11) #define SDI_DAT_FSTA 0x38 #define SDIDATFSTA_FFCNT_MASK 0x7F #define SDIDATFSTA_FFCNT(reg) (reg & SDIDATFSTA_FFCNT_MASK) #define SDIDATFSTA_RF_HALF (1 << 7) #define SDIDATFSTA_RF_FULL (1 << 8) #define SDIDATFSTA_RF_LAST (1 << 9) #define SDIDATFSTA_TF_EMPTY (1 << 10) #define SDIDATFSTA_TF_HALF (1 << 11) #define SDIDATFSTA_RF_DETECT (1 << 12) #define SDIDATFSTA_TX_DETECT (1 << 13) #define SDIDATFSTA_FAIL_NO_DETECT (0 << 14) #define SDIDATFSTA_FAIL_FIFO (1 << 14) #define SDIDATFSTA_FAIL_FIFO_LAST (2 << 14) #define SDIDATFSTA_RESET (1 << 16) #define SDI_INT_MASK 0x3C #define SDIINTMASK_RF_HALF (1<<0) #define SDIINTMASK_RF_FULL (1<<1) #define SDIINTMASK_RF_LAST (1<<2) #define SDIINTMASK_TF_EMPTY (1<<3) #define SDIINTMASK_TF_HALF (1<<4) #define SDIINTMASK_BUSY_FIN (1<<6) #define SDIINTMASK_DATA_FIN (1<<7) #define SDIINTMASK_DATA_TIMEOUT (1<<8) #define SDIINTMASK_DATA_CRC (1<<9) #define SDIINTMASK_STATUS_CRC (1<<10) #define SDIINTMASK_FIFO_FAIL (1<<11) #define SDIINTMASK_IO (1<<12) #define SDIINTMASK_READ_WAIT (1<<13) #define SDIINTMASK_RESP (1<<14) #define SDIINTMASK_CMD_TIMEOUT (1<<15) #define SDIINTMASK_CMD_SENT (1<<16) #define SDIINTMASK_RESP_CRC (1<<17) #define SDIINTMASK_NO_BUSY (1<<18) #define SDI_DAT_LI_W 0x40 /* Word access in Little Endian mode */ #define SDI_DAT_LI_HW 0x44 /* Half-Word access in Little Endian mode */ #define SDI_DAT_LI_B 0x48 /* Byte access in Little Endian mode */ #define SDI_DAT_BI_W 0x4C /* Word access in Big Endian mode */ #define SDI_DAT_BI_HW 0x41 /* Half-Word access in Big Endian mode */ #define SDI_DAT_BI_B 0x43 /* Byte access in Big Endian mode */ /* ADC */ /* XXX: ADCCON register is common to both S3C2410 and S3C2400, * but other registers are different. */ #define ADC_ADCCON 0x00 #define ADCCON_ENABLE_START (1<<0) #define ADCCON_READ_START (1<<1) #define ADCCON_STDBM (1<<2) #define ADCCON_SEL_MUX_SHIFT 3 #define ADCCON_SEL_MUX_MASK (0x7<